Solder joints with enhanced electromigration resistance

ABSTRACT

Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed.

RELATED ART

Integrated circuits may be formed on semiconductor wafers made ofmaterials such as silicon. The semiconductor wafers are processed toform various electronic devices. The wafers are diced into semiconductorchips (a chip is also known as a die), which may then be attached to asubstrate using a variety of known methods. For example, bonding padsformed on the chip may be electrically coupled to the substrate using avariety of connection approaches, including, for example, thoseutilizing solder bumps.

In one type of die attach process, a die is mounted to a substrate usinga conventional solder bump array in a flip chip configuration, using amethod known as a C4 (controlled collapse chip connection) process, inwhich solder bumps are located between the die and substrate. In a C4process, solder paste may be placed on pads on the active side of thedie, on the substrate, or on both the die and substrate, using, forexample, stencil mask printing. The solder is then melted and permittedto flow, to ensure that each bump fully wets the pad it was formed on. Adie is positioned on the bumps, and a second reflow operation is thencarried out, and a solder connection is made between the die pads andthe substrate pads. A solder connection may also be made between thepackage substrate and a printed circuit board. Solder connections may bemade between other components in an electronic assembly, including, butnot limited to, between a die and a heat spreader.

Solder materials have traditionally included alloys of tin (Sn) and lead(Pb). Lead use is being phased out due to toxicity issues. As a result,lead free solder compositions have been developed.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are described by way of example, with reference to theaccompanying drawings, which are not drawn to scale, wherein:

FIG. 1 illustrates a view of an electronic assembly including a diepositioned on a substrate, with a solder material positioned between thedie and substrate, in accordance with certain embodiments.

FIG. 2 illustrates an electronic system arrangement in which embodimentsmay find application.

DETAILED DESCRIPTION

Certain embodiments relate to formation of electronic assembliesincluding solder connections between components.

FIG. 1 illustrates an electronic assembly 10 in accordance with certainembodiments. The assembly includes a first level interconnect of asemiconductor die 12 coupled to a package substrate 14 by solder bumps16. The die 12 and the substrate 14 may each include a plurality ofbonding pads 18, 20, on which the solder bumps 16 are positioned. Thebonding pads 18, 20 may be formed from a variety of materials including,but not limited to, nickel (Ni) and copper (Cu). The assembly 10 mayalso include an underfill material 22, typically a polymer, positionedbetween the die 12 and substrate 14.

During the coupling of the die to the substrate, stresses may develop inthe die during the cool down process. If too high, these stresses canlead to failure in certain layers, such as the interlayer dielectriclayers formed on the die. In addition, depending on the materials used,electromigration may occur in the solder joint during operation.Electromigration generally refers to solid state atomic movement becauseof momentum transfer from flowing electrons, may occur in the solderjoint during operation, in particular, at high current densities. Suchmigration or movement of the metal may cause cracks, voids, solder jointseparations, or other defects to form within the interconnect structure.Excessive electromigration may lead to joint failure.

As a result, the solder used for the first level interconnect should besufficiently compliant so as to minimize stress transfer to the die, andalso have suitable electromigration properties. The solder material mayin certain embodiments be formed from a material comprising tin andcopper including one or more dopants added to impart improvedproperties, including electromigration resistance.

Certain embodiments utilize a solder material having the general formulaSn0.7Cu+X, where X is one or more dopants selected from silver (Ag),bismuth (Bi), phosphorus (P) and cobalt (Co). A SnO.7Cu solder generallyincludes about 99.3 weight percent tin and 0.7 weight percent copper.The additional dopant elements may be present in an amount of up to 2weight percent each. Certain embodiments may include at least 91 weightpercent Sn, 0.4 to 1.0 weight percent Cu, and up to 2 weight percent ofone or more of Ag, Co, Bi and P.

Although not bound by particular mechanisms, certain aspects related tothe proposed use of the dopants listed above will be discussed. It isbelieved that Ag doping can increase the energy barrier for Sndiffusion, which should help improve the electromigration properties ofthe tin based solder. It is also believed that Bi doping can help toreduce the solder joint interface defects due to its wettability withbonding pad materials such as Cu and Ni. It is also believed that P andCo doping may act to retard the growth of interfacial intermetalliccompounds and in turn decrease void generation.

Various benefits may be obtained by using more than one of the dopantsin the solder composition. Examples of embodiments utilizing Sn and Cuwith only two of the dopants include compositions consisting of (1) Sn,Cu, Ag and Co; (2) Sn, Cu, Ag and Bi; and (3) Sn, Cu, Bi, and Co. Anexample of a solder utilizing three of the dopants includes acomposition consisting of Sn, Cu, Ag, Co, and Bi. In certainembodiments, the Co dopant may be present in an amount of 1-2 weightpercent. In certain embodiments, the P dopant may be present in anamount of greater than 1 weight percent up to 2 weight percent. It isoften very difficult or impossible to prevent some level of impuritiesfrom entering the solder composition. It should be appreciated thatembodiments may include a small quantity (typically 0.1 weight percentor less) of such unavoidable impurities.

Embodiments also include methods for forming electronic devicesincluding attaching a die to a substrate. Methods may include providinga solder material on at least one of a substrate and a die, the soldermaterial comprising a composition in accordance with embodimentsdescribed above. One example includes a solder material comprising Sn,0.4 to 1.0 weight percent Cu, and at least one dopant selected from thegroup consisting of Ag, Bi, P, Co. The solder material is heated to atemperature so that it reflows. The die is coupled to the substratethrough the solder material. The solder material is solidified after thereflow. Certain embodiments, the die may be coupled to the substrateprior to the solder material being reflowed. In other embodiments, thedie may be coupled to the substrate after the solder material has beenreflowed.

Assemblies including a substrate and die joined together as describedabove may find application in a variety of electronic components. FIG. 2schematically illustrates one example of an electronic systemenvironment in which described embodiments may be embodied. Otherembodiments need not include all of the features specified in FIG. 2,and may include alternative features not specified in FIG. 2.

The system 101 of FIG. 2 may include at least one central processingunit (CPU) 103. The CPU 103, also referred to as a microprocessor, maybe a die which is attached to an integrated circuit package substrate105, which is then coupled to a printed circuit board 107, which in thisembodiment, may be a motherboard. The CPU 103 on the package substrate105 is an example of an electronic device assembly that may be formed inaccordance with embodiments such as described above. A variety of othersystem components, including, but not limited to memory and othercomponents discussed below, may also include die and substratestructures formed in accordance with the embodiments described above.

The system 101 may further include memory 109 and one or morecontrollers 111 a, 111 b . . . 111 n, which are also disposed on themotherboard 107. The motherboard 107 may be a single layer ormulti-layered board which has a plurality of conductive lines thatprovide communication between the circuits in the package 105 and othercomponents mounted to the board 107. Alternatively, one or more of theCPU 103, memory 109 and controllers 111 a, 111 b . . . 111 n may bedisposed on other cards such as daughter cards or expansion cards. TheCPU 103, memory 109 and controllers 111 a, 111 b . . . 111 n may each beseated in individual sockets or may be connected directly to a printedcircuit board. A display 115 may also be included.

Any suitable operating system and various applications execute on theCPU 103 and reside in the memory 109. The content residing in memory 109may be cached in accordance with known caching techniques. Programs anddata in memory 109 may be swapped into storage 113 as part of memorymanagement operations. The system 101 may comprise any suitablecomputing device, including, but not limited to, a mainframe, server,personal computer, workstation, laptop, handheld computer, handheldgaming device, handheld entertainment device (for example, MP3 (movingpicture experts group layer-3 audio) player), PDA (personal digitalassistant) telephony device (wireless or wired), network appliance,virtualization device, storage controller, network controller, router,etc.

The controllers 111 a, 111 b . . . 111 n may include one or more of asystem controller, peripheral controller, memory controller, hubcontroller, I/O (input/output) bus controller, video controller, networkcontroller, storage controller, communications controller, etc. Forexample, a storage controller can control the reading of data from andthe writing of data to the storage 113 in accordance with a storageprotocol layer. The storage protocol of the layer may be any of a numberof known storage protocols. Data being written to or read from thestorage 113 may be cached in accordance with known caching techniques. Anetwork controller can include one or more protocol layers to send andreceive network packets to and from remote devices over a network 117.The network 117 may comprise a Local Area Network (LAN), the Internet, aWide Area Network (WAN), Storage Area Network (SAN), etc. Embodimentsmay be configured to transmit and receive data over a wireless networkor connection. In certain embodiments, the network controller andvarious protocol layers may employ the Ethernet protocol over unshieldedtwisted pair cable, token ring protocol, Fibre Channel protocol, etc.,or any other suitable network communication protocol.

While certain exemplary embodiments have been described above and shownin the accompanying drawings, it is to be understood that suchembodiments are merely illustrative and not restrictive, and thatembodiments are not restricted to the specific constructions andarrangements shown and described since modifications may occur to thosehaving ordinary skill in the art.

1-12. (canceled)
 13. A method comprising: providing a solder material onat least one of a substrate and a die, the solder material comprisingSn, 0.4 to 1.0 weight percent of Cu, and at least one dopant selectedfrom the group consisting of Ag, Bi, P, Co; heating the solder materialto a temperature so that it reflows; coupling the die and substratetogether through the solder material; and solidifying the soldermaterial after the reflow; wherein the coupling the die and substratetogether is carried out using a method selected from the groupconsisting of: coupling the die and substrate together through thesolder prior the reflow, and coupling the die and substrate togetherthrough the solder after the solder reflow.
 14. The method of claim 13,wherein the solder material consists of: 0.4 to 1.0 weight percent Cu;greater than 0 and up to 2 weight percent Ag; greater than 0 and up to 2weight percent Co; and the balance being Sn and unavoidable impurities.15. The method of claim 14, wherein the Co is present in an amount of1.0 to 2.0 weight percent.
 16. The method of claim 13, wherein the Co ispresent in an amount of 1.0 to 2.0 weight percent.
 17. The method ofclaim 13, wherein the solder material comprises: at least 91 weightpercent Sn; 0.4 to 1.0 weight percent Cu; 0 to 2 weight percent Co;greater than 0 and up to 2 weight percent Ag; greater than 0 and up to 2weight percent Bi; and greater than 0 and up to 2 weight percent P. 18.A method comprising: providing a solder material on at least one of asubstrate and a die, the solder material comprising at least 91 weightpercent Sn, 0.4 to 1.0 weight percent Cu, and 1.0 to 2.0 weight percentCo; heating the solder material to a temperature so that it reflows;coupling the die and substrate together through the solder material; andsolidifying the solder material after the reflow; wherein the couplingthe die and substrate together is carried out using a method selectedfrom the group consisting of: coupling the die and substrate togetherthrough the solder prior the reflow, and coupling the die and substratetogether through the solder after the solder reflow.
 19. The method ofclaim 18, wherein the solder material further comprises greater than 0and up to 2 weight percent Ag.
 20. The method of claim 18, wherein thesolder material further comprises greater than 0 and up to 2 weightpercent Bi.
 21. The method of claim 18, wherein the solder materialfurther comprises greater than 0 weight percent to 2 weight percent P.22. The method of claim 19, wherein the solder material furthercomprises greater than 0 and up to 2 weight percent Bi.
 23. The methodof claim 22, wherein the solder material further comprises greater than0 and up to 2 weight percent P.